Category: AI & Robotics | Hardware Engineering | Silicon Design & Test
Employment Type: Full-Time
Location: India
Department: AI Hardware / Silicon Engineering
About the Role
Tesla’s AI Hardware team is at the forefront of revolutionising artificial intelligence through cutting-edge custom silicon. This team designs and develops advanced AI inference chips that accelerate Tesla’s machine learning capabilities — including Dojo, Tesla’s custom supercomputer built to train massive neural networks on fleet-scale video data. The chips and architectures developed by this team power the neural networks behind Full Self-Driving (FSD) and Tesla’s humanoid robot, Optimus.
Within this mission, Tesla’s Silicon Engineering team is responsible for delivering production-quality silicon from first tapeout. As a Staff DFT ATPG Engineer, you will own the full structural test lifecycle — from pre-silicon ATPG pattern generation through ATE test program development, DFT timing closure, and OSAT deployment — ensuring world-class test quality and production efficiency at massive scale.
This is a senior, high-ownership role for an engineer who wants to shape how Tesla validates the silicon that powers the future of autonomous driving and robotics.
What You Will Be Doing
ATPG Pattern Generation You will generate production-quality ATPG patterns using Tessent, covering stuck-at, transition delay, path delay, cell-aware, and small delay defect (SDD) fault models.
Coverage Optimisation You will achieve and exceed industry-leading coverage targets — greater than 99% stuck-at and greater than 98% transition coverage — while minimising pattern count to keep ATE test time efficient.
Debug & Coverage Recovery You will debug low-coverage areas including X-state sources, blocking logic, untestable faults, and ATPG abort conditions, driving them to closure.
Hybrid Bonding Test Concepts You will apply your understanding of hybrid bonding test methodologies to advanced packaging and multi-die designs.
Pattern Validation You will perform gate-level pattern simulation to validate the integrity of generated test patterns before silicon deployment.
Hierarchical & Flat ATPG Methodologies You will support both hierarchical and flat ATPG approaches for multi-million gate SoC designs, ensuring scalability across complex chip architectures.
ATE Test Program Development You will architect and develop comprehensive ATE test programs covering ATPG, MBIST, Repair, Functional, DC, and HSIO test domains.
NPI Silicon Bring-Up You will own structural test bring-up for New Product Introduction (NPI) silicon — debugging and root-causing failures through to closure.
OSAT Deployment & Optimisation You will deploy and optimise test programs at OSATs, balancing yield, quality, reliability, and cost at production scale.
Custom Test Method Development You will develop custom test methods tailored to product-specific requirements, and contribute to wafer probe and final test hardware design.
Required Qualifications
- Education: Degree in Electrical Engineering, Computer Engineering, or a related field — or equivalent practical experience
- 10+ years of experience across ATPG, ATE test development, and DFT timing
- Expert-level Tessent proficiency, including TestKompress and MemoryBIST
- Deep knowledge of fault models: stuck-at, transition, path delay, cell-aware, and SDD
- Hands-on ATE test program development and OSAT deployment experience
- SDC constraint development for DFT test modes, with timing closure using Tempus
- Ability to leverage agentic AI flows to automate ATPG and ATE test workflows
About Tesla AI Hardware
The Tesla AI Hardware team is composed of brilliant engineers and visionaries designing custom silicon and optimised architectures that keep Tesla at the forefront of AI-driven automotive and energy solutions — shaping a future where intelligent machines enhance human life. By joining this team, you’ll be directly contributing to the silicon that powers Tesla’s most ambitious AI systems, from self-driving cars to humanoid robotics.